Fully differential amplifier including common mode feedback circuit

ABSTRACT

In a fully differential amplifier so configured that an operating point potential of positive and negative output terminals of a differential amplifier having an active load is set by a common-mode feedback circuit, the common-mode feedback circuit includes a first differential pair receiving a reference potential given from an external and a positive output potential of the differential amplifier, a second differential pair receiving the reference potential and a negative output potential of the differential amplifier, and a sum current feedback device for giving a sum current of output currents of the first and second differential pairs to a bias current for the active load of the differential amplifier. With this arrangement, a difference between a common-mode output potential of the differential amplifier and the reference potential is fed back to the differential amplifier in the form of the sum current, so as to control to equalize the common-mode output potential of the differential amplifier with the reference potential.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a fully differential amplifier, andmore specifically to a fully differential amplifier so configured thatan operating point potential of positive and negative output terminalsof a differential amplifier having an active load is controlled by acommon-mode feedback circuit.

2. Description of Related Art

A common-mode feedback circuit incorporated in a fully differentialamplifier is ordinarily provided to set an operating potential ofinverted and non-inverted output terminals of the fully differentialamplifier. An example of the common-mode feedback circuit is describedin Roubik Gregorian et al "ANALOG MOS INTEGRATED CIRCUITS FOR SIGNALPROCESSING", Pages 254-256, A Wiley-Interscience Publication, 1986, thecontent of which is incorporated by reference in its entirety into thisspecification. However, this common-mode feedback circuit has only anarrow output operating range, because a number of transistors areseries-connected between a positive voltage supply line and a negativevoltage supply line. In addition, in order to freely set an outputvoltage, it is necessary to adjust the area of various circuit elements.In conclusion, this common-mode feedback circuit was very complicated indesign.

In order to improve the above mentioned common-mode feedback circuit, ithas been considered to detect a neutral point (common-mode outputpotential) between a positive output terminal and a negative outputterminal of the fully differential amplifier, to compare the detectedcommon-mode output potential with a reference potential, and to feedback the result of comparison to a control electrode of a transistorwhich constitutes an active load for the fully differential amplifier,for the purpose of equalizing the common-mode output potential with thereference potential. However, in a cascaded type of fully differentialamplifier, if a resistor is directly connected to the output terminal sothat a potential on the neutral point is detected by use of a resistorvoltage division, a gain lowers, and therefore, an advantage of thecascaded type cannot be exerted.

Under this circumstance, it has been proposed to interpose a highimpedance buffer and to detect the common-mode output potential from anoutput of the high impedance buffer by means of a voltage divisionresistor or a current addition. One typical example of this type fullydifferential amplifier will be described with reference to JapanesePatent Application Laid-open No. JP-A-01-126811, which discloses thedifferential amplifier applied with the current addition method, and thecontent of which is incorporated by reference in its entirety into thisspecification.

Referring to FIG. 1, there is shown a circuit diagram of the fullydifferential amplifier disclosed in the above identified Japanese patentapplication publication. In the shown fully differential amplifier,voltage controlled current circuits 100 and 200 are connected to outputterminals 19 and 18 of a core amplifier 500, respectively, for thepurpose of convening each output voltage into a current. The currentsthus obtained am combined by a sum current transmission circuit 300 soas to generate a sum current, which is compared at a node A with areference current generated in a reference current transmission circuit400. The result of comparison is fed back so as to control a gatevoltage of transistors Q₂₇ and Q₂₈, which constitute a portion of anactive load of the fully differential amplifier. With this feedbackoperation, the common-mode output voltage becomes equal with thereference potential V_(REF).

However, paying attention to the core amplifier 500, a connection nodebetween a drain of a transistor Q₂₃ and a source of a transistor Q₂₅ anda connection node between a drain of a transistor Q₂₄ and a source of atransistor Q₂₆ are put in a low impedance condition, since a gate ofeach of the transistors Q₂₄ and Q₂₆ are grounded. Accordingly, poles ofhigher powers caused by a parasitic capacitance are moved into a highfrequency zone, and therefore, a sufficient phase margin can be obtainedby a pole of a primary power formed by a low load capacitance C_(L). Asa result, the core amplifier can have a high cutoff frequency f_(T)suitable for a high speed operation.

However, examining the common-mode feedback circuit, poles of higherpowers in the common-mode loop are moved into a low frequency zone,because of parasitic capacitances C₁ and C₂ occurring in parallel toresistors R₁ and R₂ connected to sources of transistors Q₃₂ and Q₃₃, andbecause of a gate capacitance C₃ of gates of transistors Q₂₇ and Q₂₈which are control electrodes for applying the feedback through thecommon-mode feedback circuit. As a result, although the core amplifier500 has a sufficient phase margin, it is necessary to increase the loadcapacitance C_(L) in order to cause the common-mode feedback circuit tohave a phase margin.

This is also true in a common-mode output detection method. Namely,because of a voltage division resistor and a gate capacitance of atransistor receiving a voltage obtained by the voltage divisionresistor, poles of higher powers in the common-mode loop are moved intoa low frequency zone, with the result that the toad capacitance C_(L)must be increased for the purpose of causing the common-mode feedbackcircuit to have a phase margin.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a fullydifferential amplifier which has overcome the above mentioned defect ofthe conventional ones.

Another object of the present invention is to provide a fullydifferential amplifier having an excellent high speed operationproperty.

Still another object of the present invention is to provide a fullydifferential amplifier in which a high speed operation of a coreamplifier is not hindered by a common-mode feedback circuit.

The above and other objects of the present invention are achieved inaccordance with the present invention by a fully differential amplifierso configured that an operating point potential of positive and negativeoutput terminals of a differential amplifier having an active load isset by a common-mode feedback circuit, the common-mode feedback circuitincluding a first differential pair receiving a reference potentialgiven from an external and a positive output potential of thedifferential amplifier, a second differential pair receiving thereference potential and a negative output potential of the differentialamplifier, and a sum current feedback means for giving a sum current ofoutput currents of the first and second differential pairs to a biascurrent for the active load of the differential amplifier, so that adifference between a common-mode output potential of the differentialamplifier and the reference potential is fed back to the differentialamplifier in the form of the sum current, so as to control to equalizethe common-mode output potential of the differential amplifier with thereference potential.

The above and other objects, features and advantages of the presentinvention will be apparent from the following description of preferredembodiments of the invention with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of the conventional fully differentialamplifier;

FIG. 2 is a circuit diagram of a first embodiment of the fullydifferential amplifier in accordance with the present invention;

FIG. 3 is a circuit diagram of a second embodiment of the fullydifferential amplifier in accordance with the present invention; and

FIG. 4 is a graph illustrating phase characteristics and amplitudecharacteristics of the second embodiment of the fully differentialamplifier and the conventional fully differential amplifier.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 2, there is shown a circuit diagram of a firstembodiment of the fully differential amplifier in accordance with thepresent invention. The shown fully differential amplifier includes aninput terminal 11 for receiving an inverted phase input, and anotherinput terminal 12 for receiving a non-inverted phase input. The inputterminals 11 and 12 are connected to a gate of N-channel MOS transistorsQ₂₁ and Q₂₂, respectively, which have their sources connected in commonto a drain of an N-channel MOS transistor Q₃₁. Drains of the MOStransistors Q₂₁ and Q₂₂ are connected to drains of P-channel MOStransistors Q₂₃ and Q₂₄, respectively, which have their sourcesconnected to a high potential power supply line 13. In addition, thedrains of the MOS transistors Q₂₃ and Q₂₄ are also connected to sourcesof P-channel MOS transistors Q₂₅ and Q₂₆. respectively, whose drains areconnected to drains of N-channel MOS transistors Q₂₇ and Q₂₈,respectively, and also connected to gates of N-channel MOS transistorsQ₃₃ and Q₃₂, respectively. Sources of the MOS transistors Q₂₇ and Q₂₈are connected to drains of N-channel MOS transistors Q₂₉ and Q₃₀,respectively, which have their sources connected to a low potentialpower supply line 14.

In the above mentioned circuit, the transistors Q₂₁ to Q₃₀ constitute acore circuit of the fully differential amplifier, and the transistorsQ₂₃ and Q₂₄ constitute an active load circuit. Commonly connected gatesof the transistors Q₂₃ and Q₂₄ are supplied with a bias potential V_(B1)through a voltage terminal 15. Commonly connected gates of thetransistors Q₂₅ and Q₂₆ are supplied with a bias potential V_(B2)through a voltage terminal 16. Commonly connected gates of thetransistors Q₂₇ and Q₂₈ are supplied with a bias potential V_(B5)through a voltage terminal 20. Gates of the transistors Q₂₉, Q₃₀ and Q₃₁and also N-channel MOS transistors Q₄₄ and Q₄₅ are supplied with a biaspotential V_(B3) through a voltage terminal 17.

In addition, a positive output voltage Vo(+) and a negative outputvoltage Vo(-) are obtained from output terminals 18 and 19 connected tothe drains of the transistors Q₂₅ and Q₂₆, respectively. The positiveoutput voltage Vo(+) is compared with a reference voltage Vref by adifferential pair composed of N-channel MOS transistors Q₃₃ and Q₄₂, andthe negative output voltage Vo(-) is compared with the reference voltageVref by a differential pair composed of N-channel MOS transistors Q₃₂and Q₄₁.

Drains of the transistors Q₄₁ and Q₄₂ are connected in common to a drainand a gate of a P-channel MOS transistor Q₄₃, which has its sourceconnected to the high potential power supply line 13. Accordingly,output currents of these differential pairs are summed by the P-channelMOS transistor Q₄₃, which constitutes an active load in common to thetwo differential pairs. Drains of the transistors Q₃₂ and Q₃₃ areconnected in common to a drain and a gate of a P-channel MOS transistorQ₃₄, which has its source connected to the high potential power supplyline 13. Sources of the transistors Q₄₁ and Q₃₂ are connected in commonto a drain of the transistor Q₄₄, and sources of the transistors Q₄₂ andQ₃₃ are connected in common to a drain of the transistor Q₄₄. Source ofthe transistors Q₄₄ and Q₄₅ are connected to the low potential powersupply line 14.

In addition, P-channel MOS transistors Q₄₆ and Q₄₇ are connected inparallel to the transistors Q₂₃ and Q₂₄, respectively. Drains of thetransistors Q₄₆ and Q₄₇ are connected in common to the drain of thetransistors Q₄₃.

Now, a feedback operation of the above mentioned circuit will bedescribed. Now, general consideration will be made on a differentialamplifier composed of MOS transistors (for example, in FIG. 2, thetransistors Q₃₂ and Q₄₁ connected in the form of a differential pair,and the transistor Q₄₃ constituting the active load, and the N-channelMOS transistor Q₄₄ acting as a constant current source). As described infor example. C. Toumazou et al, "Analog IC design: the current-modeapproach", Page 183 and Pages 235-238, Peter Peregrinus Ltd., 1990, thecontent of which is incorporated by reference in its entirety into thisspecification, the relation between an output current I₀₁ (the currentflowing through the transistor Q₄₃) and an input voltage differenceV_(id) (the difference between the reference potential Vref and theinverted phase output Vo(-) of the core amplifier) is expressed asfollows:

    I.sub.01 =(2·I.sub.SS ·K).sup.1/2 ·V.sub.id ·{1-[(K/2)·I.sub.SS ]·V.sub.id.sup.2 }.sup.1/2

where 2·I_(SS) is the current flowing through the transistor Q₄₄ whichconstitutes the constant current source, and K is defined as follows:

    K=μ·C.sub.ox ·W/{2·(1+δ)·L}

where

μ=carrier mobility of MOS transistor

C_(ox) =gate oxide film capacitance per unit area

W=channel width

L=channel length

δ=correction coefficient (≈0)

In the above equation, {1-[(K/2)·I_(SS) ]·V_(id) ² }^(1/2) is an evenfunction with respect to V_(id), and therefore. I₀₁ is an odd functionwith respect to V_(id). In addition, this output current I₀₁ is notlinear in relation to the input voltage difference V_(id). However, inthe case that a deviation of the common-mode output potential, namely,of a 1/2 potential of the sum of the non-inverted phase output and theinverted phase output of the core amplifier including the transistorsQ₂₁ and Q₂₂ is small, it is possible to constitute, in the followingmanner, a feedback loop having, as the amount of feedback, thedifference between the reference potential Vref and the common-modeoutput potential, by utilizing the fact that I₀₁ is the odd functionwith respect to V_(id).

In the circuit shown in FIG. 2, consider the two differential pairscomposed of the MOS transistors Q₃₂ and Q₄₁ and the MOS transistors Q₃₃and Q₄₂, respectively. When the reference voltage Vref is equal to thecommon-mode output voltage, assuming that the input voltage differencein the differential pair composed of the MOS transistors Q₃₂ and Q₄₁ isV_(id), the input voltage difference in the differential pair composedof the MOS transistors Q₃₃ and Q₄₂ becomes -V_(id). Accordingly, theoutput currents I₀₁ and I₀₂ of the two differential pairs, which are anodd function with respect to their input voltage difference, havepolarities opposite to each other, and therefore, cancel out each other.Therefore, the sum current I₀ (the current flowing through thetransistor Q₄₃, namely, I₀₁ +I₀₂) does not change, similarly to the caseof no input. In other words, no adverse influence is given to a normaloperation.

If the reference potential Vref becomes different from the common-modeoutput potential, for example, when the common-mode output potentialbecomes higher than the reference potential Vref, the current of thetransistor Q₄₃ decreases. In this case, since a linear operation can beapproximated in a small output amplitude region, it is possible todetect the difference between the reference potential and thecommon-mode output potential with no problem. On the other hand, thelinear operation cannot be approximated in a large output amplituderegion. However, if the potential difference ΔV between the referencepotential and the common-mode output potential is small as compared withthe amplitude, it is sufficient if a differentiated coefficient in theamplitude is considered. Here, since the differentiated coefficient ofthe odd function is an even-function, differentiations of the respectiveoutput currents of the above mentioned two differential pairs which havelo opposite polarities but are the same in absolute value, become equal.Accordingly, the sum current of the output currents caused by thepotential difference ΔV is in proportion to the potential difference ΔV.Here, precisely, since the differentiated coefficient is different ifthe amplitude is different, the amount of feedback varies dependentlyupon the amplitude. However, since the loop gain in the feedback loop issufficiently large, influence to the non-inverted output and theinverted output can be neglected. Thus, the feedback loop having as theamount of feedback the difference between the reference potential Vrefand the common-mode output potential, is constituted.

In the circuit shown in FIG. 2, the transistors Q₄₃, Q₄₆ and Q₄₇constitute a current mirror circuit, and drains of the transistors Q₄₆and Q₄₇ are connected to the drains of the transistors Q₂₃ and Q₂₄,respectively. Accordingly, if the current of the transistors Q₄₃decreases, the currents of the transistors Q₄₆ and Q₄₇ correspondinglydecrease, so that the bias current of the core amplifier decreases, andtherefore, the common-mode output potential decreases.

If the common-mode output potential becomes lower than the referencepotential Vref, a similar consideration may result. Namely, the feedbackoperation is performed to elevate the common-mode output potential sothat the common-mode output potential becomes equal to the referencepotential Vref.

Now, poles of higher powers in the common-mode loop will be examined. Inthis embodiment, since no resistor is used for detecting the common-modeoutput potential, differently from the conventional fully differentialamplifier, there is no influence caused by a parasitic capacitanceoccurring in parallel to a resistor. In addition, the feedback of thecommon-mode feedback circuit is applied in the form of a current by thecurrent mirror circuit, the circuit is not influenced by a gatecapacitance of the transistor (constituting the control electrode).

In the circuit shown in FIG. 2, attention will be paid to a connectionnode N₁ between the drain electrodes of the transistor Q₄₃ and the drainelectrodes of the transistor Q₄₁ and Q₄₂, and a connection node N₂between the drain electrodes of the transistor Q₃₄ and the drainelectrodes of the transistor Q₃₂ and Q₃₃. A resistance at the respectiveconnection nodes N₁ and N₂ are made to 1/g_(m) (where g_(m) istransconductance) by the transistors Q₄₃ and Q₃₄, respectively, andtherefore, are constituted to have a low resistance. Namely, it would beunderstood that it is put in a low impedance condition. Accordingly,poles of higher powers caused by a parasitic capacitance will be movedinto a high frequency zone. This is also true at a connection nodebetween each differential pair and its current source. Examining aconnection node between the constant current source transistor Q₄₄ andthe drain electrodes of the transistor Q₃₂ and Q₄₁, and a connectionnode between the constant current source transistor Q₄₅ and the drainelectrodes of the transistor Q₃₃ and Q₄₂, since the reference potentialVref is a fixed potential, it can be regarded from the viewpoint of therespective connection nodes that the transistors Q₄₁ and Q₄₂ are in agate-grounded fashion, namely, have a low input impedance. Therefore,the respective connection nodes are put in a low input impedancecondition.

Now, a second embodiment of the fully differential amplifier inaccordance with the present invention will be described with referenceto FIG. 3, which is a circuit diagram of the second embodiment. In FIG.3, elements corresponding to those shown in FIG. 2 are given the sameReference Numerals, and explanation thereof will be omitted.

As will be seen from comparison between FIGS. 2 and 3, the secondembodiment is characterized in that the transistors Q₂₃, Q₂₄, Q₄₆ andQ₄₇ are consolidated or simplified into two transistors Q₂₃ and Q₂₄. Thetransistors Q₂₃ and Q₂₄ constitutes a current mirror circuit incooperation with the transistor Q₄₃ through which the sum current of thetwo differential pairs of the common-mode feedback circuit flows.

Similarly to the first embodiment, respective connection nodes in thesecond embodiment are constituted in a low impedance condition which isnot influenced by parasitic capacitances.

Referring to FIG. 4, there is shown phase characteristics and theamplitude characteristics (gain) in the second embodiment of the fullydifferential amplifier in accordance with the present invention and inthe conventional fully differential amplifier shown in FIG. 1, whichwere obtained from a simulation based on a SPICE (Simulation Programwith Integrated Circuit Emphasis). In FIG. 4, the axis of ordinatesshows the phase and the gain, and the axis of abscissas indicates thefrequency. In addition, the solid lines represent the phasecharacteristics, and the two-dot chain lines show the amplitudecharacteristics. In both of the solid lines and the two-dot chain lines,an upper solid line and an upper two-dot chain line indicate the secondembodiment of the present invention, and a lower solid line and a lowertwo-dot chain line indicate the conventional fully differentialamplifier shown in FIG. 1.

It will be seen from FIG. 4 that the embodiment of the present inventionhas a phase margin on the order of 30° to 40°, but the phase margin ofthe conventional fully differential amplifier is almost 0° when the samelead capacitance is given. Namely, since it cannot be said that a givencircuit is stable if the phase margin is on the order of a few degrees,the conventional fully differential amplifier had to be constructed tohave an increased lead capacitance for the purpose of stabilizing theoperation. However, the embodiment of the present invention has nonecessity for an increased lead capacitance, and therefore, it ispossible to realize a fully differential amplifier which has a highcutoff frequency f_(T) and which therefore is suitable for a high speedoperation.

As mentioned above, in the fully differential amplifier in accordancewith the present invention, the common-mode output potential is detectedby addition in the current mode, and fed back to the core amplifier inthe current mode. In other words, the common-mode feedback circuit isconstituted of the two differential pairs and the current minor circuit.Accordingly, the respective connection nodes in the common-mode feedbackcircuit are maintained in the low impedance condition, and therefore,the circuit is not influenced by a parasitic capacitance. In addition,since poles of higher powers caused by a parasitic capacitance are movedinto a high frequency zone, a sufficient phase margin can be obtained bya pole of a primary power created by a low load capacitance.

Thus, the present invention can overcome the disadvantage of theconventional fully differential amplifier in which although a coreamplifier has a sufficient phase margin, a common-mode feedback circuithad to have an increased load capacitance for the purpose of having aphase margin, with the result that a high speed operation was inevitablysacrificed. In other words, the present invention makes it possible toprovide a fully differential amplifier which has a high cutoff frequencyf_(T) and which therefore is suitable for a high speed operation, sincethe fully differential amplifier in accordance with the presentinvention can be stabilized without increasing the load capacitance.

The invention has thus been shown and described with reference to thespecific embodiments. However, it should be noted that the presentinvention is in no way limited to the details of the illustratedstructures but changes and modifications may be made within the scope ofthe appended claims.

I claim:
 1. A fully differential amplifier, comprising:a differentialamplifier having positive and negative output terminals; a common-modefeedback circuit for setting an operating point potential of saidpositive and negative output terminals of said differential amplifierhaving an active load, said common-mode feedback circuit including:afirst differential pair for receiving a reference potential given froman external source and a positive output potential of said differentialamplifier; a second differential pair for receiving said referencepotential and a negative output potential of said differentialamplifier; and a sum current feedback means for producing a sum currentof output currents of said first and second differential pairs to a biascurrent for said active load of said differential amplifier, so that adifference between a common-mode output potential of said differentialamplifier and said reference potential is fed back to said differentialamplifier in the form of the sum current, so as to controllably equalizethe common-mode output potential of said differential amplifier withsaid reference potential, wherein said sum current feedback meansincludes:a first transistor connected to said first and seconddifferential pairs as a common active load, second and third transistorsconnected to said differential amplifier as an active load, and fourthand fifth transistors connected in parallel to said second and thirdtransistors, respectively, said first, fourth and fifth transistorsbeing connected to constitute a current mirror circuit.
 2. A fullydifferential amplifier, comprising:a differential amplifier havingpositive and negative output terminals; a common-mode feedback circuitfor setting an operating point potential of said positive and negativeoutput terminals of said differential amplifier having an active load,said common-mode feedback circuit including:a first differential pairfor receiving a reference potential given from an external source and apositive output potential of said differential amplifier; a seconddifferential pair for receiving said reference potential and a negativeoutput potential of said differential amplifier; and a sum currentfeedback means for producing a sum current of output currents of saidfirst and second differential pairs to a bias current for said activeload of said differential amplifier, so that a difference between acommon-mode output potential of said differential amplifier and saidreference potential is fed back to said differential amplifier in theform of the sum current, so as to controllably equalize the common-modeoutput potential of said differential amplifier with said referencepotential, wherein said sum current feedback means includes:a firsttransistor connected to said first and second differential pairs as acommon active load; and second and third transistors connected to saiddifferential amplifier as an active load, said first, second and thirdtransistors being connected to constitute a current mirror circuit.
 3. Afully differential amplifier comprising:a first input terminal forreceiving an inverted phase input; a second input terminal for receivinga non-inverted phase input; first and second output terminals foroutputting a pair of complementary output signals; a core circuitincluding a first N-channel MOS transistor having a gate connected tosaid first input terminal, a second N-channel MOS transistor having agate connected to said second input terminal, said first and secondN-channel MOS transistors having their sources commonly connected to oneend of a current source having its other end grounded, the core circuitfurther including an active load having first and second P-channel MOStransistors which have their source connected to a high potential powersupply line, drains of said first and second P-channel MOS transistorsbeing connected to drains of said first and second N-channel MOStransistors, respectively, gates of said first and second P-channel MOStransistors being commonly connected, the core circuit further includingthird and fourth P-channel MOS transistors which have their sourceconnected to said drains of said first and second P-channel MOStransistors, respectively, drains of said third and fourth P-channel MOStransistors being connected to said first and second output terminals,respectively, and also connected to ground through a pair of currentsources, gates of said third and fourth P-channel MOS transistors beingcommonly connected to receive a predetermined bias voltage; a firstdifferential pair composed of third and fourth N-channel MOStransistors, a drain of said third N-channel MOS transistor beingconnected to a drain and a gate of a fifth P-channel MOS transistor,which has its source connected to said high potential power supply line,a drain of said fourth N-channel MOS transistor being connected to adrain and a gate of a sixth P-channel MOS transistor, which has itssource connected to said high potential power supply line, sources ofsaid third and fourth N-channel MOS transistors being commonly connectedto one end of a current source having its other end grounded, a gate ofsaid third N-channel MOS transistor being connected to said first outputterminal, and a gate of said fourth N-channel MOS transistor beingconnected to a reference voltage, so that a positive output voltage onsaid first output terminal is compared with said reference voltage; asecond differential pair comprising:fifth and sixth N-channel MOStransistors, a drain of said fifth N-channel MOS transistor beingconnected to said drain and said gate of said fifth P-channel MOStransistor, a drain of said sixth N-channel MOS transistor beingconnected to said drain and said gate of said sixth P-channel MOStransistor, sources of said fifth and sixth N-channel MOS transistorsbeing commonly connected to one end of a current source having its otherend grounded, a gate of said fifth N-channel MOS transistor beingconnected to said second output terminal, and a gate of said sixthN-channel MOS transistor being connected to said reference voltage, sothat a negative output voltage on said second output terminal iscompared with said reference voltage, said drains of said fourth andsixth N-channel MOS transistors being connected to control a currentflowing through said active load, so that a difference between acommon-mode output potential of said differential amplifier and saidreference potential is fed back to said differential amplifier in theform of a sum current, so as to controllably equalize the common-modeoutput potential of said differential amplifier with said referencepotential.
 4. A fully differential amplifier as claimed in claim 3,wherein said drains of said fourth and sixth N-channel MOS transistorsare connected to said commonly connected gates of said first and secondP-channel MOS transistors.
 5. A fully differential amplifier as claimedin claim 3, wherein said commonly connected gates of said first andsecond P-channel MOS transistors are connected to a common fixed biasvoltage, andwherein said drains of said fourth and sixth N-channel MOStransistors are connected to commonly-connected gates of seventh andeighth P-channel MOS transistors which have their source connected tosaid high potential power supply line and their drains connected to saiddrains of said first and second P-channel MOS transistors, respectively.6. A fully differential amplifier as claimed in claim 3, wherein saidcommonly-connected gates of said first and second P-channel MOStransistors are connected to a common fixed bias voltage.
 7. A fullydifferential amplifier as claimed in claim 6, wherein said drains ofsaid fourth and sixth N-channel MOS transistors are connected to acommonly-connected gates of seventh and eighth P-channel MOS transistorswhich have their source connected to said high potential power supplyline and their drains connected to said drains of said first and secondP-channel MOS transistors, respectively.
 8. A fully differentialamplifier as claimed in claim 3, wherein said drains of said fourth andsixth N-channel MOS transistors are connected to a commonly-connectedgates of seventh and eighth P-channel MOS transistors which have theirsource connected to said high potential power supply line and theirdrains connected to said drains of said first and second P-channel MOStransistors, respectively.